[動腦益智] CLOCK and Details TRANSITIONS

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The SDA pin is nor-mally pulled large with an exterior gadget. Knowledge around the SDApin might modify only all through SCL lower time periods (refer toData Validity timing diagram).

Details variations during SCLhigh intervals will indicate a start out or cease affliction asdefined beneath.Get started Affliction: A high-to-low transition of SDA withSCL significant is often a get started ailment which have to precede any othercommand (check with Start off and Quit Definition timing dia-gram).

Stop Affliction: A low-to-high changeover of SDA withSCL higher is really a halt condition which terminates all communi-cations. Following a read through sequence, the end command willplace the EEPROM within a standby ability mode (make reference to Startand Stop Definition timing diagram).

Acknowledge: All addresses and details words and phrases are seri-ally transmitted to and in the EEPROM in 8-bit text.Any device on the technique bus acquiring knowledge (when com-municating along with the EEPROM) will have to pull the SDA bus lowto accept that it's got efficiently gained eachword.

This need to occur throughout the ninth clock cycle aftereach word obtained and just after all other process gadgets havefreed the SDA bus. The EEPROM will similarly acknowl-edge by pulling SDA lower following receiving just about every tackle ordata term (consult with Accept Reaction from Receivertiming diagram).

STANDBY Manner: The AT24C01 features a small powerstandby method and that is enabled: (a) upon power-up and (b)just after the receipt of the Stop little bit along with the completion of anyinternal functions.

MEMORY RESET: Soon after an interruption in protocol, powerloss or program reset, any 2-wire component is usually reset by follow-ing these waysa) Clock as many as nine cycles, (b) appear for SDA superior in every cyclewhile SCL is high after which (c) make a begin ailment asSDA is superior.

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